34 .name =
"riscv_uart1" },
40 .driver_data =
NULL },
66 for (
pfn_t pfn = 0; pfn < total_npages; pfn += STEP)
void platform_pml3e_set_flags(pml3e_t *pml3, vm_flags flags)
void platform_pml3e_set_huge(pml3e_t *pml3e, pfn_t pfn)
@ CONSOLE_CAP_READ
console supports read
@ CONSOLE_CAP_EXTRA_SETUP
extra setup required
void interrupt_handler_register(u32 irq, irq_serve_t handler, void *data)
Register an interrupt handler.
#define ALIGN_UP(addr, size)
#define container_of(ptr, type, member)
void plic_enable_irq(u32 irq)
pml3e_t * pml3_entry(pml3_t pml3, ptr_t vaddr)
pml3_t pml4e_get_or_create_pml3(pml4e_t *pml4e)
pml4e_t * pml4_entry(pml4_t pml4, ptr_t vaddr)
#define write_csr(reg, val)
const char __riscv64_trap_entry[]
#define SSTATUS_FS_INITIAL
bool serial_console_setup(console_t *console)
bool serial_console_irq_handler(u32 irq, void *data)
const serial_driver_t riscv64_uart_driver