1// SPDX-License-Identifier: GPL-3.0-or-later
2
3#include "mos/x86/cpu/cpu.h"
4
5#include "mos/platform/platform.h"
6#include "mos/platform/platform_defs.h"
7#include "mos/syslog/printk.h"
8#include "mos/x86/cpu/cpuid.h"
9
10#include <mos_string.h>
11
12// clang-format off
13#define do_static_assert(feat) MOS_STATIC_ASSERT(X86_CPUID_LEAF_ENUM(feat) >= 0);
14#define test_ensure_all_leaves_are_supported(feature) do_static_assert(CPU_FEATURE_##feature)
15FOR_ALL_CPU_FEATURES(test_ensure_all_leaves_are_supported)
16#undef test_ensure_all_leaves_are_supported
17#undef do_static_assert
18// clang-format on
19
20void x86_cpu_initialise_caps(void)
21{
22 platform_cpuinfo_t *cpuinfo = &per_cpu(platform_info->cpu)->cpuinfo;
23 memzero(s: cpuinfo, n: sizeof(platform_cpuinfo_t));
24
25#define impl_fill_leaf(_l, _sl, _r) cpuinfo->cpuid[X86_CPUID_LEAF_ENUM(_l, _sl, _r, _)] = x86_cpuid(_r, _l, _sl);
26 FOR_ALL_SUPPORTED_CPUID_LEAF(impl_fill_leaf);
27#undef impl_fill_leaf
28
29 MOS_ASSERT_X(cpu_has_feature(CPU_FEATURE_FSGSBASE), "FSGSBASE is required");
30 MOS_ASSERT_X(cpu_has_feature(CPU_FEATURE_FXSR), "FXSR is required");
31 MOS_ASSERT_X(cpu_has_feature(CPU_FEATURE_SSE), "SSE is required");
32 MOS_ASSERT_X(cpu_has_feature(CPU_FEATURE_XSAVE), "XSAVE is required");
33
34 x86_cpu_set_cr4(x86_cpu_get_cr4() | BIT(7) | BIT(11) | BIT(16)); // set CR4.PGE, CR4.FSGSBASE, CR4.UMIP
35}
36
37void x86_cpu_setup_xsave_area(void)
38{
39 pr_dinfo2(x86_startup, "setting up xsave area...");
40
41 reg_t cr0 = x86_cpu_get_cr0();
42 cr0 &= ~BIT(2); // clear coprocessor emulation CR0.EM
43 cr0 |= BIT(1);
44 x86_cpu_set_cr0(cr0);
45
46 reg_t cr4 = x86_cpu_get_cr4();
47 cr4 |= BIT(9) | BIT(10) | BIT(18); // set CR4.OSFXSR, CR4.OSXMMEXCPT and CR4.OSXSAVE
48 x86_cpu_set_cr4(cr4);
49
50 reg_t xcr0 = XCR0_X87 | XCR0_SSE; // bit 0, 1
51 size_t xsave_size = 512; // X87 + SSE
52
53 // SSE
54 xcr0 |= XCR0_SSE; // bit 1
55 xsave_size += 64; // XSAVE header
56
57 // AVX
58 if (cpu_has_feature(CPU_FEATURE_AVX))
59 xcr0 |= XCR0_AVX;
60
61 static const char *const xcr0_names[] = {
62 [0] = "x87", //
63 [1] = "SSE", //
64 [2] = "AVX", //
65 [3] = "MPX BNDREGS", //
66 [4] = "MPX BNDCSR", //
67 [5] = "AVX-512 OPMASK", //
68 [6] = "AVX-512 ZMM0-15", //
69 [7] = "AVX-512 ZMM16-31", //
70 [8] = "PT", //
71 [9] = "PKRU", //
72 };
73
74 for (size_t state_component = 2; state_component < 64; state_component++)
75 {
76 reg32_t size, offset, ecx, edx;
77 __cpuid_count(0xd, state_component, size, offset, ecx, edx);
78 if (size && offset && ((ecx & BIT(0)) == 0))
79 {
80 const char *const name = state_component < MOS_ARRAY_SIZE(xcr0_names) ? xcr0_names[state_component] : "<unknown>";
81 pr_dinfo2(x86_startup, "XSAVE state component '%s': size=%d, offset=%d", name, size, offset);
82
83 if (xcr0 & BIT(state_component))
84 {
85 pr_dcont(x86_startup, " (enabled)");
86 xsave_size += size;
87 }
88 }
89 }
90
91 pr_dinfo2(x86_startup, "XSAVE area size: %zu", xsave_size);
92
93 __asm__ volatile("xsetbv" : : "c"(0), "a"(xcr0), "d"(xcr0 >> 32));
94 platform_info->arch_info.xsave_size = xsave_size;
95}
96