1// SPDX-License-Identifier: GPL-3.0-or-later
2
3#include "mos/x86/cpu/cpuid.hpp"
4
5#include <mos/types.h>
6
7#pragma once
8
9#define MOS_PLATFORM_PAGING_LEVELS 4 // PML4, PDPT, PD, PT
10#define MOS_USER_END_VADDR 0x00007FFFFFFFFFFF
11#define MOS_KERNEL_START_VADDR 0xFFFF800000000000
12
13#define MOS_PLATFORM_HAS_FDT 0
14
15#define PML1_SHIFT 12
16#define PML1_MASK 0x1FFL // 9 bits page table offset
17#define PML1_ENTRIES 512
18
19#define PML2_SHIFT 21
20#define PML2_MASK 0x1FFL // 9 bits page directory offset
21#define PML2_ENTRIES 512
22#define PML2_HUGE_CAPABLE 1 // 2MB pages
23
24#define PML3_SHIFT 30
25#define PML3_MASK 0x1FFL // 9 bits page directory pointer offset
26#define PML3_ENTRIES 512
27#define PML3_HUGE_CAPABLE 1 // 1GB pages
28
29#define PML4_SHIFT 39
30#define PML4_MASK 0x1FFL // 9 bits page map level 4 offset
31#define PML4_ENTRIES 512
32#define PML4_HUGE_CAPABLE -1
33
34#define MOS_ELF_PLATFORM EM_X86_64
35
36#define MOS_PLATFORM_PANIC_INSTR "ud2"
37
38// clang-format off
39#define MOS_PLATFORM_PANIC_POINT_ASM \
40 ".quad 1b\n\t" \
41 ".quad %c0\n\t" \
42 ".quad %c1\n\t" \
43 ".quad %c2\n\t"
44// clang-format on
45
46// clang-format off
47#define MOS_PLATFORM_DEBUG_MODULES(X) \
48 X(x86_cpu) \
49 X(x86_lapic) \
50 X(x86_ioapic) \
51 X(x86_startup) \
52 X(x86_acpi)
53// clang-format on
54
55#define MOS_PLATFORM_MEMORY_BARRIER() __asm__ __volatile__("" ::: "memory")
56
57typedef struct _platform_process_options
58{
59 bool iopl;
60} platform_process_options_t;
61
62typedef struct _platform_thread_options
63{
64 ptr_t fs_base, gs_base;
65 u8 *xsaveptr;
66} platform_thread_options_t;
67
68typedef struct _platform_cpuinfo
69{
70 x86_cpuid_array cpuid;
71} platform_cpuinfo_t;
72
73typedef struct _platform_arch_info
74{
75 ptr_t rsdp_addr;
76 u32 rsdp_revision;
77} platform_arch_info_t;
78